Renesas Electronics /R7FA6M4AF /OSPI /DCSR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DCSR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DALEN0DMLEN0 (0)ACDV 0CMDLEN 0 (0)DAOR 0ADLEN0 (0)DOPI 0 (0)ACDA 0 (0)PREN

DOPI=0, DAOR=0, ACDA=0, ACDV=0, PREN=0

Description

Device Command Setting Register

Fields

DALEN

Transfer data length setting

DMLEN

Dummy cycle setting

ACDV

Access Device setting

0 (0): Send commands to device 0.

1 (1): Send commands to device 1.

CMDLEN

Transfer command length setting

DAOR

Data order setting

0 (0): byte0, byte1, byte2, byte3

1 (1): byte1, byte0, byte3, byte2

ADLEN

Transfer address length setting

DOPI

DOPI single byte setting

0 (0): Each cycle has two bytes data. (normal DOPI mode)

1 (1): Each cycle has one byte data. (The byte data changes at the rising edge of the clock and does not change at the falling edge of the clock.)

ACDA

Data Access Control

0 (0): Register access Do not arrange the transfer data.

1 (1): Data access

PREN

Preamble bit enable for OctaRAM

0 (0): No check preamble bit from OctaRAM

1 (1): Check preamble bit from OctaRAM

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